This paper presents the design architecture, simulation and measurement result of a stable high-performance on-chip signal generator system. The system consists of an ultra-low-power Voltage controlled oscillator designed for the frequency range of 7.2−8.2GHz and is interfaced with a divide-by-2 prescaler. The circuit generates an RF output of 3.6 GHz to 4.1 GHz with constant average output power and phase-noise (PN). The minimum current consumption of the VCO core is 1.05 mA at a supply voltage of 250 mV and a back gate voltage of 1.4 V. The back gate bias is adapted in the RF block to minimize the DC power consumption and enhance the PN and the output power.    «

This paper presents the design architecture, simulation and measurement result of a stable high-performance on-chip signal generator system. The system consists of an ultra-low-power Voltage controlled oscillator designed for the frequency range of 7.2−8.2GHz and is interfaced with a divide-by-2 prescaler. The circuit generates an RF output of 3.6 GHz to 4.1 GHz with constant average output power and phase-noise (PN). The minimum current consumption of the VCO core is 1.05 mA at a supply voltage...    »