Scaling limitations of the conventional MOSFETs demand need for novel ideas and devices. A serious problem with scaling conventional MOSFETs is the enhanced junction tunneling leakage currents due to the non-scalability of the junction electric fields. To overcome this problem, devices based on tunneling currents have been proposed where tunneling currents are no longer an unwanted parasitic effect. The tunnel FET, a three terminal gated p-i-n diode is one such device, originally proposed in III-V compounds and later on silicon. Both lateral as well as vertical structures have been experimentally demonstrated. Even though the devices have very low leakage current, highly suitable for low power applications, the on-current observed is several orders of magnitude less than the industry requirements. Further, detailed study of this device has not been done and it is not understood as to how they behave with scaling. Since the device has different current flow mechanism, it follows different parameter definitions and scaling rules in comparison to the conventional MOSFETs. In this thesis, using 2-dimensional computer device simulations, a basic understanding of tunnel FETs is developed. A simulation based model is also developed to describe the current-voltage characteristics and to define the electrical parameters of these devices. Since the tunneling currents are weakly dependent on temperature, it is shown that the subthreshold swing is independent of the thermal voltage, kT/q, and hence can be scaled to below this limit. It is further predicted that unlike the conventional MOSFETs, the subthreshold swing is not a constant but is a strong function of the gate bias and can be vanishingly small within a small range of gate bias. Thus, it is shown that with proper choice of device geometry parameters, the current can increase several orders of magnitude within a small range of gate bias. Thus, it becomes critical to optimize these devices in the subthreshold region, and gate workfunction is shown to play a critical role. As low on-currents are observed for silicon tunnel FETs, two optimization schemes are proposed to enhance the tunnel FET on-state performance using SiGe. In the first method pseudomorphically strained SiGe is used to lower the tunnel barrier width to enhance the on-state performance, while in the second method, SiGe is used to lower the tunnel barrier height to enhance the performance. Both the methods have certain advantages as well as disadvantages and a detailed investigation of both the methods is presented. A less than kT/q room temperature subthreshold swing is further predicted. Experimental verification of the simulation-based model, exponentially increasing transfer characteristics for both the n-channel as well as p-channel operating modes, off-currents less than 100 fAmikrom for sub-100 nm channel length devices, and kT/q independent and gate bias dependent subthreshold swing are experimentally verified. Furthermore, using experimental data, a quality assessment parameter for the tunnel FETs is identified. The forward-biased gated p-i-n diode shows gate induced tunneling currents, resulting in a peak in the forward-differential current. The simulations predict that the peak vanishes for sharper and high source and drain doping profiles, which also result in improved performance for the tunnel FETs. Due to the extremely low leakage currents, saturation in the output characteristics for sub-100 nm channel length devices, exponentially increasing transfer characteristics for both the sub-threshold as well as the on-region of operation, temperature independent current-voltage characteristics and kT/q independent subthreshold swing, the tunnel FETs look very promising for future scaled CMOS technologies, for both ultra low power and high speed applications.    «

Scaling limitations of the conventional MOSFETs demand need for novel ideas and devices. A serious problem with scaling conventional MOSFETs is the enhanced junction tunneling leakage currents due to the non-scalability of the junction electric fields. To overcome this problem, devices based on tunneling currents have been proposed where tunneling currents are no longer an unwanted parasitic effect. The tunnel FET, a three terminal gated p-i-n diode is one such device, originally proposed in III...    »