This paper presents a system architecture to enable partial reconfiguration (PR) on Intel/Altera FPGAs in small cloud-like environments. The system facilitates multi-user access to FPGA resources through a central server and lightweight API communication, aiming to simplify remote usage and lower technical entry barriers. Implementation and testing on the Terasic Han Pilot Platform validate basic functionality, including bitstream deployment and dynamic interaction with PR regions. The architecture relies on standard Linux environments and Python-based tooling, making it suitable for educational or research settings. The framework is released as open source to facilitate reuse and further development. The proposed approach provides a foundation for exploring scalable and vendor-agnostic FPGA infrastructures in academic contexts and for integrating PR in remote FPGA labs.     «

This paper presents a system architecture to enable partial reconfiguration (PR) on Intel/Altera FPGAs in small cloud-like environments. The system facilitates multi-user access to FPGA resources through a central server and lightweight API communication, aiming to simplify remote usage and lower technical entry barriers. Implementation and testing on the Terasic Han Pilot Platform validate basic functionality, including bitstream deployment and dynamic interaction with PR regions. The architect...     »