The realization of large-scale quantum processing units (QPUs) demands that superconducting Qubit fabrication evolve from laboratory methods to industrially scalable, CMOS-compatible technologies. Current lift-off-based fabrication lacks the reproducibility and throughput required for million-Qubit architectures. To address this challenge, this work establishes a fully CMOS-compatible process for superconducting Qubits on 200mm wafers and systematically investigates the influence of individual process steps on device performance and coherence. Superconducting materials such as aluminum (Al) and titanium nitride (TiN) were examined with respect to deposition, etching, and surface treatment parameters. Correlations between process conditions and resonator quality factors were identified, revealing that etching power has a dominant influence on dielectric losses. A major challenge of this work was the realization of all-aluminum Josephson junctions using a double dry etch approach, enabling precise junction definition and full CMOS compatibility. Multiple fabrication approaches were investigated with the selected one exhibit high wafer-scale uniformity with 92.8 % yield and 12.4 % junction resistance variation for a target critical current of 24.2 nA and frequency of 4.42 GHz. Various surface treatment and passivation methods were evaluated to suppress reoxidation and improve resonator quality. Selective oxide removal using HF vapor and phosphoric acid increased compared to bare Al resonators the quality factors by nearly a factor of four to QTLS ≈ 2.8 × 10^6. In addition, novel approaches were developed to correlate room-temperature (RT) wafer-level measurements with cryogenic benchmarking. Parameters such as Qubit capacitance, substrate leakage current, and junction breakthrough voltage (VBT) were identified as potential RT indicators for cryogenic performance. In particular, a strong correlation between VBT and the Qubit relaxation time T1 suggests the possibility of predicting coherence without extensive cryogenic testing. Overall, this work demonstrates that high-quality superconducting Qubits can be fabricated in a CMOS-compatible 200mm process, providing a foundation for scalable and industrially viable quantum hardware.     «

The realization of large-scale quantum processing units (QPUs) demands that superconducting Qubit fabrication evolve from laboratory methods to industrially scalable, CMOS-compatible technologies. Current lift-off-based fabrication lacks the reproducibility and throughput required for million-Qubit architectures. To address this challenge, this work establishes a fully CMOS-compatible process for superconducting Qubits on 200mm wafers and systematically investigates the influence of individual p...     »