This paper presents a structured approach to teaching digital system design through the development of a RISC-V processor on FPGA hardware. The described course guides students from combinatorial and sequential circuits to a pipelined CPU, integrating hardware description language design, simulation, and debugging. Emphasizing constructive alignment and hands-on learning, the curriculum bridges the gap between theoretical instruction and practical implementation, enabling students to understand and verify CPU behavior at the hardware–software boundary. Through progressive lab tasks, students gain proficiency in VHDL, digital design methodology, and system-level reasoning while engaging with industry-standard EDA tools such as Intel Quartus Prime and ModelSim. Course evaluations demonstrate increased student motivation while improving conceptual understanding of processor architecture. The proposed framework serves as a blueprint for incorporating open architectures such as RISC-V into modern engineering education. Evaluation revealed that the continuous oral exam format and feedback loops were effective in identifying misconceptions and reinforcing long-term learning outcomes. These changes led to higher student engagement, which in turn resulted in an elimination of exam retakes, while grades remained stable, showing that "weaker" students are successfully integrated and supported without lowering overall academic standards.     «

This paper presents a structured approach to teaching digital system design through the development of a RISC-V processor on FPGA hardware. The described course guides students from combinatorial and sequential circuits to a pipelined CPU, integrating hardware description language design, simulation, and debugging. Emphasizing constructive alignment and hands-on learning, the curriculum bridges the gap between theoretical instruction and practical implementation, enabling students to understand...     »